The following documents are available for download to provide you additional product information:

  • White Paper - "The Formal Verification of Design Constraints"

  • White Paper - "Delay Safe False Paths"

  • STARC Presentation at JEDAT EDA Fair 2010- "SDC Merge Advantage using FishTail"

  • DAC User Track Presentation 2009 - "The Automatic Generation of Merged-Mode Design Constraints"

  • Mode Merging Case Study - "Cutting P&R Runtimes in Half by Merging Modes into Super Modes"

To obtain access to these documents, please complete the following information:

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