The following documents are available for download:

  • White Paper - "Constraint Management"

  • A discussion of our solution for constraint mapping, promotion, demotion and equivalence verification

  • White Paper - "Constraint Verification"

  • A discussion of our formal and assertion-based constraint verification solution

  • White Paper - "Constraint Generation"

  • A discussion of our constraint generation capabilities

  • White Paper - "RTL Glitch Verification"

  • A whitepaper on our glitch verification solution

  • White Paper - "Mode Merging"

  • A discussion of our mode-merging solution

  • White Paper - "Delay Safe False Paths"

  • How do we ensure that all the exceptions we verify are safe from glitches

  • Formal Verification of MBIST MCPs

  • A joint Mentor Graphics/FishTail paper on the verification of MBIST MCPs

  • DAC User Track Presentation 2017 - "Significantly Improving Place & Route Runtime by Minimizing Clocks/Register"

  • Presentation from TI that describes how they improved P&R runtimes by 3x by using FishTail Focus to reduce clocks per registers

  • DAC User Track Presentation 2017 - "Achieving ROI through an Automated Hybrid Approach to Timing Exception Verification"

  • Presentation from Mediatek describing how they used FishTail's Formal + ABV methodology to catch real bugs without noise

  • STARC Presentation at JEDAT EDA Fair 2010 - "SDC Merge Advantage using FishTail"

  • Presentation from STARC summarizing their study of our mode merging solution

  • DAC User Track Presentation 2009 - "The Automatic Generation of Merged-Mode Design Constraints"

  • Presentation from TI summarizing their experience using our mode merging solution

  • Mode Merging Case Study - "Cutting P&R Runtimes in Half by Merging Modes into Super Modes"

  • Customer experience using our mode merging solution in P&R

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