FishTail is in the process of building a first-class organization to provide leading-edge solutions to ASIC and FPGA designers. Employees will receive competitive compensation, stock options and health benefits. We are looking for employees who are looking to make a significant and visible impact in an often intense - though always exciting - start-up environment.

We are currently looking for people to fill the positions listed below. To apply please e-mail your resume to jobs@fishtail-da.com.

Title: Sr. R&D Engineer

Job Responsibilities:
This position will require developing software to integrate FishTail products with third-party software components. It will require understanding an existing body of C++ code and taking ownership of the code. It will require working on user-interface related code.

Job Requirements:
The engineer will need to have strong C++ software implementation skills. Prior experience in using the Standard C++ library (STL) is required. Experience with software development tools (gdb, purify, etc.) on a Linux platform is required. Strong algorithmic skills and knowledge of graph traversal algorithms is required. Our products deal with large amounts of data and so developing software that is high-performance and is efficient in its memory utilization is key. Prior knowledge of digital design and EDA tools is preferred. Prior knowledge of System Verilog is preferred. The ideal candidate will have an M.S. in Computer Science and prior EDA software development experience. Prior startup experience is strongly preferred. This position requires working out of our corporate headquarters at Lake Oswego, Oregon.

Title: Field Applications Engineer

Job Responsibilities:
Primary responsibility is to provide customer support. Will be expected to perform product presentations and demonstrations, answer inquiries, manage evaluations, and generally assure that customers have a positive experience and gain a full understanding of the capabilities and benefits of FishTail’s products for the generation, verification and management of timing constraints. Technical tasks will include generating and verifying timing exceptions using FishTail’s products, importing these constraints into major chip-implementation tool suites, resolving any integration issues, and obtaining metrics on design QoR improvement. Will interact with R&D by providing product requirements, bug reports, etc. Must help develop applications notes, white papers, and other technical materials. Some travel will be required.

Job Requirements:
Must have at least 5 years of ASIC or FPGA design experience, with a strong understanding of the RTL to GDS-II chip implementation flow. Must have served in an application engineering or equivalent role for an EDA vendor for at least 3 years. Must have strong familiarity with static timing and synthesis tools such as PrimeTime and Design Compiler, be able to write and interpret synthesizable Verilog, and have a good understanding of SDC constraint files, including defining false paths and multi-cycle paths for a chip. Prior experience with logic synthesis and/or place & route tools is required. BS/MS degree in Electrical Engineering, Computer Science or equivalent is required. We have open positions based out of San Jose and San Diego/Irvine, California.