12-01-09		IC Journal		Taking Exception: Verifying and Generating False and Multi-Cycle Path Constraints There is a newcomer in this arena, however, a company with the picturesque name of Fishtail. They have a Confirm product that will validate exceptions that the user creates. But this is actually only one of a three-piece suite of tools.
07-29-09		DAC 2009		The Automatic Generation of Merged-Mode Design Constraints Focus helped reduce constraint development cycle-time by a factor of 2-3X. Focus helped in catching implementation bugs that could have been missed in conventional verification.
07-23-09		Electronic Design		46th DAC Is This July's San Francisco Treat FishTail Design Automation has worked with Texas Instruments to create new technology and a flow for the automated generation of merged-mode design constraints.
07-16-09		FishTail		FishTail to Spotlight Automated Generation of Merged-Mode Constraints at DAC Its all new at the FishTail booth.
03-19-08		FishTail		STARC Endorses FishTail for Timing Exception Verification and Generation FishTail Tools Demonstrate Ability to Generate and Verify Timing Exceptions on Multi-Million Gate Design.
10-17-07		FishTail		FishTail Expands its Sales and Support Operations in Asia Company signs JEDAT as its exclusive distributor in Japan and opens India Office.
05-17-07		FishTail		FishTail Lays Down the Gauntlet at 2007 DAC Customers have the opportunity to verify and generate timing exceptions (false and multi-cycle paths) on their designs on-the-spot at the show.
10-18-06		FishTail		FishTail and Mentor Graphics Collaborate on False Path Verification Flow FishTail's Refocus product interfaces with Mentor's FastScan and TestKompress products to exhaustively verify false-paths at the gate-level.
06-26-06		EE Times		Cooley Census Highlights Feedback from eight respondents about FishTail's design constraint synthesis product, Focus, was nearly unanimous in praise of the tool.
06-23-06		Deepchip		DeepChip Congratulates FishTail I am VERY impressed with this technology and with this company. They are some very bright folks, and they are dedicated to the success of their customers. "They have taken a very difficult problem and provided a pragmatic solution. Anyone using timing exceptions and not using Fishtail is playing with fire." "We use it in our flow and have found Fishtail's Focus tool is well worth the money. In our last tapeout, it caught 6 user defined exceptions which were wrongly declared, hence probably saving us a chip revision." "We are using Fishtail on almost all of our chips and see significant benefits in terms of speed improvements. We are consistently observing reduction in negative slack when using FP's alone.
02-07-06		TechOnLine		Design Constraint Solutions Circa 2006: Where's the Value? The real value in design constraint automation tools is in the synthesis of false paths associated with multiple clock modes, the synthesis of functional false and multi-cycle paths and the verification of user-specified multi-cycle paths.
01-25-06		Deepchip		Successful Customer Tapeout using FishTail for False-Path Synthesis and for Verification of User Multi-Cycle Paths Over 5 blocks, the Focus tool discovered about 5,000 false paths in a cumulative run time of about 7 hours. All of the false paths were proven using 0-in at the RTL level and PrimeTime at the gate-level. We also used FishTail to verify our existing user-defined MCPs. Focus found errors in few of our user-specified MCPs; all of which were removed from our final constraint file. We just taped out this chip and our experience with the FishTail tools has been very positive.
01-25-06		FishTail		STARC Standardizes on FishTail for Timing Exception Generation FishTail Tools Demonstrate 50% Timing Slack Improvement in Latest STARC Production Flow
01-24-06		EE Times		EDA Companies Tout Involvement with Japan's STARC STARC's latest production flow, the STARCAD-21 Flow version 3.0, would include Fishtail's technology for timing exception generation.
06-02-05		FishTail		FishTail To Showcase Rapid Timing Exception Generation, Gate-Level and RTL Exception Verification at DAC (booth #2152)
05-25-05		FishTail		Interra Systems Facilitates Successful Deployment of Focus Interra Systems, a leading provider of software building blocks for the electronic design automation industry, announced successful integration of its Verilog (CheetahTM) and VHDL (JaguarTM) analyzers into the Focus product line offered by FishTail Design Automation.
05-18-05		FishTail		FishTail Joins Synopsys in-Sync Program FishTail Design Automation today announced that it has joined the Synopsys, Inc., in-Sync Program to provide customers with complete interoperability between FishTail's Focus product and Synopsys Design Compiler and PrimeTime products.
05-11-05		EE Times		FishTail joins two Mentor partner programs FishTail Design Automation Inc. has joined Mentor Graphics Corp.'s OpenDoor and ModelSim Value Added Partnership programs.
05-11-05		FishTail		FishTail Joins Mentor Graphics OpenDoor Program and the ModelSim Value Added Partnership Program FishTail Design Automation today announced that it has joined both Mentor Graphics (Nasdaq:MENT) OpenDoor Program and the ModelSim Value Added Partnership Program. The memberships will provide joint customers with integration between FishTail's Focus and Mentor Graphics 0-In and ModelSim products.
05-04-05		EE Times		FishTail granted patent for technology underlying products FishTail Design Automation Inc. said Wednesday (May 4, 2005) that the technology underlying its automated timing constraint generation products has been granted a patent by the U.S. Patent Office. FishTail said the patent encompasses the ability to generate timing exceptions such as false paths and multi-cycle paths from synthesizable design descriptions.
05-04-05		FishTail		FishTail Granted Patent for the Automatic Generation of Timing Exceptions from Synthesizable RTL FishTail Design Automation announced today that it has been issued patent 6,877,139 by the United States Patent Office. The new patent, titled Automated approach to constraint generation in IC design, encompasses the ability to generate timing exceptions (false paths and multi-cycle paths) from synthesizable design descriptions.
02-16-05		FPGA Journal		The Impact of Timing Exceptions on FPGA Performance An article by our own James Henson in the FPGA Journal about how timing exceptions can make a speed grade or more difference to FPGA performance.
02-16-05		EE Times		DAC 'Trip Report' Highlights Fishtail's Focus, a tool that generates false and multicycle paths, won strong support.
02-09-05		Deepchip		Deepchip turns the focus on FishTail We use FishTail Focus for almost all of our designs. We find that the quality of the netlist improves dramatically. My overall impression was that it was very fast, incredibly simple to use (scripted), and basically worked as advertised. Fishtail does work and points out the correct false paths and multicycle paths. 32-bit executable for Focus can handle huge designs as big as 5 million gates.
12-30-04		EE Times		FishTail one of the Top Ten EE Design stories of 2004 Of the hundreds of EE design news stories posted in 2004, which received the most readership? This article reveals what readers regarded as important and interesting.
09-17-04		EE Times		FishTail helps EDA raise $175,000 for cancer research Venture capitalists, bankers, chip designers and EDA executives up to raise over $175,000 for cancer research at a fundraiser dinner-auction held in San Jose.
09-08-04		FishTail		FishTail Expands its Sales and Support Operations around the Globe; signs distributors in Europe and Southeast Asia
08-24-04		FishTail		0-In Welcomes FishTail Design Automation to its Check-In Partner Program FishTail and 0-In collaborate to leverage industry's leading formal verification tools to prove static timing constraints
05-19-04		FishTail		FishTail Design Automation Signs Toshiba's System LSI Division Toshiba cites significant productivity improvement and area reduction as key factors in choosing Focus.
03-15-04		EE Times		Tool pinpoints false paths, steers designers away "allowing timing analysis and closure in a more formal way"
03-08-04		EE Times		Timing constraints should be generated up front "Is the surest way to a push-button chip-implementation flow through a design methodology that requires the upfront automated generation and verification of timing exceptions?"
01-22-04		EE Times		DAC "trip report" evaluates EDA tools "Several engineers raved about FishTail's Focus product"
01-20-04		Deepchip		DAC'03 Trip Report item 16 FishTail Focus "one of the Best of DAC'03 Tools to Check Out." "I really see it as a breakthrough methodology" "I estimate it'll reduce months in the schedule for timing exceptions to no more than 2 weeks."
10-28-03		EE Times		Designers share tips at Magma user conference "The partner paper that drew the most interest and questions"
10-22-03		Deepchip		Report on the Magma Users Group Meeting "a new tool so when you run P&R you are only trying to close timing on the real constraints"