ADVISORY

FishTail To Showcase Rapid Timing Exception Generation, Gate-Level
and RTL Exception Verification at DAC (booth #2152)

Portland, Oregon, June 2, 2005 – FishTail Design Automation, Inc., the golden timing constraints company, today announced what it will be highlighting at the 2005 Design Automation Conference in Anaheim, California, June 13-16 at the Anaheim Convention Center, booth #2152.

FishTail will demonstrate how automatically generated timing exceptions make the difference:

  1. between meeting and not meeting timing;


  2. between spending weeks trying to close timing in the back-end vs. getting it done in a few hours;


  3. between chip failures because of incorrect timing exceptions vs. first-pass success.


ASIC and FPGA design and implementation engineers are invited to see live demonstrations of the company’s Focus™ product for the generation of timing exceptions on VHDL, Verilog and mixed-language designs, the Assertions Package for the verification of Focus generated and user-specified timing exceptions and Refocus™ for the integration of timing exceptions into gate-level netlists. To schedule a live suite demonstration, please register at the FishTail website at http://fishtail-da.com/dac_reg/main.php Seating is limited, so please register early.

FishTail Customers Weigh in With Feedback
To read what customers have to say about the use of Focus, view the report on DeepChip at http://www.deepchip.com/items/0445-04.html. To see what’s new with the FishTail tools visit http://www.fishtail-da.com/dac_reg/whatsnew.pdf.

About Focus
FishTail's Focus™ product solves the time-consuming problem of poor chip-implementation results because of missing or incorrect timing exceptions by formally identifying false and multi-cycle paths early in the design cycle before virtual prototyping and logic synthesis. In addition, Focus also generates assertions that justify why a false-path or multi-cycle path definition is correct. Using only the synthesizable description and clock definitions, Focus automatically generates the timing exceptions for the design in standard SDC file format for use by downstream implementation tools.

About FishTail Design Automation
Founded in 2002, FishTail Design Automation has set its sights on tackling the difficult problem of precise constraints on chip timing – the area where the success or failure of a design is ultimately determined. The company’s patented technology improves chip implementation by automatically identifying exceptions to single-cycle clocking from RTL descriptions. FishTail is privately funded. For more information about FishTail and Focus, please visit the company’s website at www.fishtail-da.com.

FishTail and the Focus are trademarks of FishTail Design Automation, Inc. All other brand names and product names are the property of their respective owners.

For more information, contact:

Barbara Marker for FishTail
HighPointe Communications
503-209-2323
Barbara@hipcom.com
 



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