FishTail Granted Patent for the Automatic
Generation of Timing Exceptions from Synthesizable RTL
Portland, Oregon - May 4, 2005 – FishTail Design Automation, the
golden timing constraints company, announced today that it has been issued
patent 6,877,139 by the United States Patent Office. The new patent,
titled “Automated approach to constraint generation in IC design,”
encompasses the ability to generate timing exceptions (false paths and
multi-cycle paths) from synthesizable design descriptions.
Previous approaches have attempted to identify false paths at the
gate-level and have inevitably run into computational limits. The
fundamental innovation that FishTail has brought to the marketplace is the
ability to quickly discover false and multi-cycle paths on large and
complex designs by examining their RTL descriptions. While the patent is
not limited to a specific approach to timing exception generation, the
Focus™ product from FishTail automatically identifies the control logic on
a design and performs a functional abstraction of the non-control portions
of a design. Functional abstraction ensures that the downstream formal
analysis of the design to identify false and multi-cycle paths is fast and
memory efficient.
“The patent that has been awarded to us confirms what our customers
acknowledged when we launched the Focus product early last year - that we
have achieved a fundamental technical breakthrough in the EDA industry,”
said Ajay Daga, founder and CEO at FishTail Design Automation. “We are the
only game in town when it comes to a production-ready tool for the
generation of timing exceptions on multi-million gate designs. Our
products are being used worldwide with great success by major
semiconductor and networking companies.” Customer data on the impact of
Focus generated timing exceptions may be viewed at FishTail’s website.
See also quality of results page:
Quality of Results Data
About Focus
FishTail's Focus™ product solves the time-consuming problem of poor
chip-implementation results because of missing or incorrect timing
exceptions by formally identifying false and multi-cycle paths early in
the design cycle - before virtual prototyping and logic synthesis. In
addition, Focus also generates assertions that justify why a false-path or
multi-cycle path definition is correct. Using only the synthesizable
description and clock definitions, Focus automatically generates the
timing exceptions for the design in standard SDC file format for use by
downstream implementation tools.
About FishTail Design Automation
Founded in 2002, FishTail Design Automation has set its sights on tackling
the difficult problem of precise constraints on chip timing – the area
where the success or failure of a design is ultimately determined. The
company’s patent-pending technology improves chip implementation by
automatically identifying exceptions to single-cycle clocking from RTL
descriptions. FishTail is privately funded. For more information about
FishTail and Focus, please visit the company’s website at
www.fishtail-da.com.
For more information, contact:
Barbara Marker for FishTail
HighPointe Communications
503-209-2323
Barbara@hipcom.com |
