PRESS RELEASE
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FishTail to Spotlight Automated
Generation of Merged-Mode Constraints at DAC It�s all new at the Portland, Oregon, July 16, 2009 � New Merged-Mode Constraint
Generation Technology The progression of the new technology will continue at the
FishTail booth, where DAC attendees will view demonstrations of its
application to a back-end design flow. In a back-end flow, FishTail�s Focus� tool takes as input multiple SDC files
and a gate-level netlist, and the output generated
is a single merged-mode constraint file that encapsulates timing requirements
for all of the individual mode-specific SDC files. FishTail engineers will
explain the tradeoffs that engineers can make to obtain pessimistic, but
simple merged-mode constraint files for driving place-and-route and accurate,
but more complex constraint files for timing signoff. New SDC Equivalence
Checking Technology FishTail will also be demonstrating new technology for
checking the equivalence between SDC files. FishTail�s
SDC equivalence checker allows engineers to establish if the impact of a
constraint file as applied to one version of a design is equivalent to the impact
of another constraint file as applied to another version of the design. The
impact of a constraint file refers to the manner in which registers on a
design are clocked and the scope of timing exceptions. Similar to logical
equivalence checking, SDC equivalence checking allows engineers to ensure
that a signoff constraint file constrains the design in the same way as the
golden constraint file used as input to the implementation flow. New Technology for Constraint
Promotion In addition, FishTail will be demonstrating new technology
for the creation of chip-level constraints from block-level constraints. FishTail�s Refocus� product promotes block-level
constraints up to the chip-level and then pushes these constraints to the
boundary of the chip to create a chip-level constraint file. Conflicts
between block-level constraints and any existing chip-level constraints are
flagged. This technology is useful for system-on-a-chip (SoC)
integration teams that need to create an SoC constraint file but only have IP constraints to work
with. New Constraint Debugging
Environment Finally, FishTail will be demonstrating a new constraint
debugging environment that allows engineers to understand how clocks
propagate in a design and how clock-muxes and
clock-gates control clock propagation. The constraint debugging environment
allows engineers to understand the scope of timing exceptions in terms of the
clock-crossings and timing paths constrained by an exception. This helps
establish if a timing exception is written more loosely than it should have
been and how it might be tightened up. �The theory is that you innovate your way through a
downturn so you are well poised to gain market share when the economy turns
around,� said Ajay Daga, CEO, FishTail Design
Automation. �That is exactly what we have done. Over the past year we have
made the most significant extensions to our technology portfolio from the
time we first launched our products for exception generation. We have taken
our product offering into completely new aspects of constraint creation,
verification and management.� To schedule a demonstration, please visit FishTail�s website. About
FishTail Design Automation Founded in 2002, FishTail
Design Automation has set its sights on tackling the difficult problem of
precise constraints on chip timing � the area where the success or failure of
a design is ultimately determined.� The
company�s patented technology improves chip implementation by automatically verifying,
generating and managing design constraints. FishTail is privately funded. For
more information about FishTail, please visit the company�s website at www.fishtail-da.com. For
more information, contact: Barbara Benjamin for FishTail HighPointe
Communications 503-209-2323 |
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