STARC Standardizes on FishTail for
Timing Exception Generation
FishTail Tools Demonstrate 50% Timing Slack Improvement in Latest
STARC Production Flow Portland, Oregon, January 25,
2006 – FishTail Design Automation, Inc., the golden timing constraints
company, today announced that Japan’s Semiconductor Technology Academic
Research Center (STARC) will release a new production flow for chip
implementation using FishTail’s technology for timing exception
generation. The STARCAD-21 Flow Version 3.0 includes the use of FishTail
products to improve implementation Quality of Results (QoR) and Turn
around Time (TAT).
STARC engineers conducted extensive evaluations of the Focus™ and Refocus™
products from FishTail on real customer designs. Several different
methodologies for the integration of the timing exceptions generated by
Focus into logic and physical synthesis tools were considered before
making the final flow recommendation. On a 500K gate microprocessor design
from one of STARC’s member companies, the new flow demonstrated
substantial improvement in chip timing over what was previously obtained
using user constraints. The total negative slack for the design improved
from 70ns to 33ns and the worst negative slack dropped from -0.5ns to
-0.3ns. This improvement was made possible by the detailed false paths
generated by the Focus product, all of which were verified to be correct
using a variety of exception verification tools and methodologies.
“We are enthusiastic in our endorsement of FishTail’s products for the
generation of timing exceptions," said Nobuyuki Nishiguchi, Vice
President, General Manager Development Dept.-1 of STARC. "Our detailed
study has clearly shown that the use of FishTail exceptions in the
chip-implementation flow will provide substantial improvement in design
QoR and TAT."
“Our close partnership with STARC has resulted in the development of a
flow that will benefit not only engineers in Japan but those worldwide,”
stated Ajay Daga, founder and CEO of FishTail. “The pain experienced by
chip-implementation engineers in trying to get a chip to timing closure
while working with an incomplete constraint set is real and recurring. Our
proven ability to unambiguously address this pain makes our suite of tools
for the generation and verification of timing exceptions an absolute must
for high-performance chip design.”
About Focus
FishTail's Focus™ product solves the time-consuming problem of poor
chip-implementation results because of missing or incorrect timing
exceptions by formally identifying false and multi-cycle paths early in
the design cycle before virtual prototyping and logic synthesis. In
addition, Focus also generates assertions that justify why a
user-specified false-path or multi-cycle path definition is correct. Using
only the synthesizable description and clock definitions, Focus
automatically generates the timing exceptions for the design in standard
SDC file format for use by downstream implementation tools.
About FishTail Design Automation
Founded in 2002, FishTail Design Automation has set its sights on tackling
the difficult problem of precise constraints on chip timing – the area
where the success or failure of a design is ultimately determined. The
company’s patented technology improves chip implementation by
automatically identifying exceptions to single-cycle clocking from RTL
descriptions. FishTail is privately funded. For more information about
FishTail and Focus, please visit the company’s website at
www.fishtail-da.com.
FishTail and the Focus are trademarks of FishTail Design Automation, Inc.
All other brand names and product names are the property of their
respective owners.
For more information, contact:
Barbara Marker for FishTail
HighPointe Communications
503-209-2323
Barbara@hipcom.com
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