False paths and multi-cycle paths are a big problem when trying to reach timing closure. Chip design teams today rarely specify complete timing exceptions at the start of the chip implementation flow. Instead, these constraints are added piecemeal, late in the design cycle, adding time, uncertainty and risk - just as you're trying to tape-out.

FishTail solves this problem with a suite of products for timing constraint generation, verification and management. FishTail's timing constraint generation product Focus takes RTL or netlist as input and generates clocks, generated clocks, input/output delays, false and multi-cycle paths for a chip. Focus also pushes chip-level constraints down to the block-level. FishTail's Confirm product takes RTL and design constraints as input and formally establishes whether the design is fully and correctly constrained. Confirm reports missing clocks or input/output delays, conflicting case analyses, and incorrect false and multi-cycle paths. Finally, FishTail provides a constraint management product Refocus, that maps golden design constraints to evolving versions of a gate-level netlist as a design is taken through different chip-implementation steps. Refocus also promotes block-level constraints to the chip-level.

With FishTail's suite of products for constraint generation, verification and management, design teams are empowered to implement better quality chips with greater confidence in much less time!