IC design is not getting any easier. With increased gate counts, higher clock speeds, smaller chip sizes and reduced power requirements, designers have a very difficult task. Today's virtual prototyping and chip-implementation tools are powerful and address several key deep-sub micron issues, but there remains a fundamental conundrum. Precise constraints on chip timing, upon which the design ultimately succeeds or fails, remain in a state of flux throughout the design cycle. False paths and multi-cycle paths are typically entered only in response to timing problems. As timing problems seriously manifest themselves only during place & route, this is late in the design cycle to be tweaking your fundamental timing goals. All of this results in extra timing closure iterations, the risk of silicon failure because of incorrect user-specified timing exceptions, chips that consume more area and power than they should, and a messy handoff from chip design to implementation teams. FishTail Design Automation has developed ground-breaking, patented technology to solve this problem, reducing design cycle time, reducing risk and improving design quality.
 

FishTail's constraint generation product, Focus, starts with the RTL description for a design. Focus generates a template clock definition file that specifies the ports and pins on the design on which clocks and generated clocks should be defined. The template constraint file also specifies input/output delays by establishing the clocks used to constrain paths to and from the ports on a design. A converter from sdc to xls and back allows users to view the template constraints in Excel, change clock names, periods, i/o budgets, scale values for different corners etc. Once the clock and i/o constraints are in place Focus is used to generate clock groups for the design. Focus analyzes the clock generation logic and the clock crossings on a design to establish which clocks are exclusive to each other, whether the clocks are logically or physically exclusive, whether clock sense commands are required to control clock propagation. With the correct clocks, i/o constraints, clock groups and clock senses in place a significant milestone on constraint quality is achieved in a matter of minutes or hours and well before any serious chip implementation work commences. Optionally, Focus can also be used to generate timing exceptions (false and multi-cycle path definitions). False paths generated by Focus result from the manner in which combinatorial control logic affects the flow of information on a chip. Multi-cycle paths generated by Focus result from the use of control logic to cause additional clock cycles to be inserted when propagating information from one register to another. All timing exceptions generated by Focus are delay-safe and so it is impossible under any circuit delay situation to propagate a glitch through a Focus generated false or multi-cycle path that will cause timing failure. Focus generated timing exceptions can be filtered using third-party synthesis or STA tools to yield a handful of timing-critical exceptions that will improve design timing, reduce area and power. Finally, Focus is used to merge multi-mode constraint files into a single super-mode constraint file. The objective being to cut P&R runtimes by half using the super-mode constraint file in P&R when compared to multi-mode P&R.

FishTail’s constraint verification product, Confirm, reads in the RTL and user-written design constraints. Confirm is a separate product from Focus and uses a separate body of code, different algorithms to verify design constraints. Confirm is first used to verify clock constraints (unclocked registers, missing or incorrect generated clock definitions, missing or incorrect clock groups, clock reconvergence, issues with clock propagation, etc.). Confirm also flags missing i/o constraints and conflicting case analysis values. Once the clock, case analysis and i/o constraints are clean Confirm is used to formally establish if all the paths constrained by a timing exception are indeed false or multi-cycle. Confirm only considers a timing exception to be correct if it is delay-safe. Confirm provides complete information on each timing exception, pointing out all the paths that are correctly constrained by a single exception and those that are incorrect. Users provide Confirm architectural information to take into account static configuration registers on a design and how they are programmed, or debug endpoints that do not need to meet timing, or SVA assertions that forbid certain combinations of signal values. The objective is to use Confirm to get to the milestone where all paths constrained by all exceptions are flagged as passing. When Confirm flags an issue a powerful HTML based debug environment is used to understand and resolve the issue. This HTML environment uses inter-process communication to display paths, waveforms and objects in graphical debugging environments like Verdi. Confirm also supports an assertion-based verification flow for timing exception verification. With this flow, Confirm is used to generate an assertion for an exception that does not pass formal proof. The assertion states the property that needs to be satisfied for a timing exception to be correct. The assertions generated by Confirm are imported into functional simulation tools and verified by running the RTL regressions for the design.

FishTail’s constraint management product, Refocus, is used to map the golden timing constraints for a design to gate-level netlists generated by each step of the implementation flow. The intent is to maintain a single repository of design constraints and to use Refocus to map these golden constraints to the netlist as it evolves through the chip-implementation flow. Refocus also maps gate-level constraints up to RTL, accounting for name changes and hierarchy flattening during the implementation flow. Refocus’s ability to bring gate-level signoff constraints up to RTL allows easy verification of signoff constraints against an RTL design representation. Refocus also promotes IP constraints to the chip-level, allowing IP designers to maintain a single standalone view of their constraints and have an automated tool generated a promoted representation for use at the chip-level. Finally, Refocus is used to establish equivalence between two different constraint files as applied to the same design, or the same constraint file applied to two different logically equivalent representations of the design. The SDC equivalence check capability in Refocus is useful to establish if the constraints applied to a post-route netlist constrain the design in the same way as the constraints applied to a pre-layout netlist.

For more information on FishTail products, please:

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